1. Field of the Invention
The subject invention relates generally to the field of semiconductor device fabrication and, more specifically, to the fabrication of an integral capacitor structure in a semiconductor device.
2. Description of the Art
The fabrication of a semiconductor wafer to create a semiconductor integrated circuit device typically involves a sequence of processing steps that fabricate the multi-layer structure of integrated circuits comprising integrated circuit components generally associated with the integrated circuit device. Such processing steps may include (1) the deposition of metals, dielectrics, and semiconductor films on the semiconductor wafer, (2) the creation of masks by lithography techniques, (3) the doping of semiconductor layers by diffusion or implantation, (4) the polishing of various layers (e.g. chemical-mechanical polishing), and (5) the etching of various layers for selective or blanket material removal.
Semiconductor integrated circuits are typically fabricated by a layering process in which several layers of material are applied on or in a surface of a wafer, or on or in a surface of a previous layer. These layers can constitute a metal pattern forming various elements of an electrical circuit. Insulating material and dielectric material are added at various stages of the fabrication process. The layers are typically treated to create a smooth, planar surface.
In forming a semiconductor device, one common practice has been to use deposition techniques to apply a particular layer to an existing substrate or layer. In one type of process, such as vapor deposition, reactant gas(s) in a carrier gas, are provided through a tube wherein the gas(s) reacts with the wafer. In a typical vapor deposition process, the thickness of the thin film layer is measured following completion of the deposition. Under these circumstances, the film thickness is generally controlled by the amount of time that the device is exposed to the vapor deposition process. The subsequent measurement of the film thickness is often accomplished in a xe2x80x9cgo/no-goxe2x80x9d manner in which devices having a film thickness falling outside a predetermined thickness range are rejected and scrapped. In other cases, the semiconductor device is returned for further processing, either for additional material deposition, or for material removal such as in a polishing process. Ordinarily, the economics of mass production mitigate in favor of simply scrapping the component.
During the fabrication process, a portion or portions of a layer may be removed. This may be accomplished by chemical mechanical polishing (CMP). CMP is used to selectively remove a portion or portions of a layer of the semiconductor device and/or remove a portion or portions of substrate of the semiconductor device. Typically, a CMP planarization of a wafer involves holding the wafer against a rotating polishing pad that is subjected to a slurry such as a silica-based alkaline slurry. The polishing pad also applies pressure against the wafer.
While it is desirable to use CMP planarization during the fabrication of semiconductor devices, the CMP planarization step may present some problems and drawbacks. For example, each additional CMP step leads to additional costs and additional processing time in the semiconductor fabrication process.
Additionally, a CMP step on a newly formed layer on the wafer may cause alignment targets thereon to lose their steps after the CMP method is performed. The CMP planarization step may also lead to xe2x80x9cover polishingxe2x80x9d (i.e. removal of material that was not intended to be removed). All of the above results may contribute to defective devices, loss of device yield, and lack of device reliability.
In view of the above, it is desirable to form constituent parts and/or components of a semi-conductor device with as little additional steps as possible. Such constituent parts and/or components include transistors, capacitors, and the like.
What is therefore needed in view of the above, is a system, method and/or apparatus for fabricating multiple components of a semi-conductor device during a common step of the fabrication process.
What is therefore further needed in view of the above is a system, method and/or apparatus for fabricating a capacitor of a semi-conductor device at the same time as fabrication of at least a portion of a transistor of the semi-conductor device.
The subject invention comprises a system, process and/or apparatus for forming a capacitor during fabrication of a semiconductor device. Particularly, the subject invention comprises a system, process and/or apparatus for forming a capacitor during fabrication of a transistor of a semiconductor device. More particularly, the subject invention comprises a system, process and/or device for forming a capacitor during fabrication of a gate electrode of a transistor of a semiconductor device. Even more particularly, the subject invention comprises a system, process and/or apparatus for forming an integrated capacitor at the same time as fabrication of a gate electrode of a transistor by polishing. Still more particularly, the subject invention comprises a system, process and/or apparatus for forming an integrated capacitor during fabrication of a gate electrode of a transistor employing chemical mechanical polishing (CMP). In one form, capacitor and gate formation utilize an oxide polish stop layer during CMP thereof. In another form, capacitor and gate formation utilize a nitride polish stop layer during CMP thereof.
In one form thereof, the subject invention provides a method of fabricating a capacitor on a substrate. The method includes the steps of: (a) etching at the same time a gate electrode region for a transistor and a first capacitor electrode region on a capacitor foundation formation on the substrate; (b) depositing a first conductive material in the etched gate electrode region and in the etched first capacitor electrode region; (c) performing chemical mechanical polishing of the conductive material to yield a gate electrode and a first capacitor electrode; (d) depositing a dielectric layer over the gate electrode and the first capacitor electrode; (e) etching a second capacitor electrode region in the dielectric layer; (f) depositing a capacitor dielectric material and second conductive material in the etched second capacitor electrode region; and (g) performing chemical mechanical polishing of the second conductive material to yield a second capacitor electrode, the first and second capacitor electrodes and the capacitor dielectric layer forming a capacitor.
In a further form of the above method, the capacitor foundation formation includes an oxide layer, and the step of performing chemical mechanical polishing of the conductive material to yield a gate electrode and a first capacitor electrode utilizes the oxide layer as a polish stop.
In another further form of the above method, the capacitor foundation formation includes a nitride layer, and the step of performing chemical mechanical polishing of the conductive material to yield a gate electrode and a first capacitor electrode utilizes the nitride layer as a polish stop.
In another form thereof, the subject invention provides a method of fabricating a capacitor on a substrate. The method includes the steps of: (a) performing capacitor foundation formation on the substrate; (b) depositing polish stop layer material on the capacitor foundation and the substrate; (c) etching a first capacitor electrode region on the capacitor foundation formation and a transistor gate region on the substrate; (d) depositing a first conductive material in the etched first capacitor electrode region and the transistor gate region; (e) performing chemical mechanical polishing on the deposited first conductive material to yield a gate electrode and a first capacitor electrode; (f) depositing a dielectric material over the gate electrode and the first capacitor electrode; (g) etching a second capacitor electrode region in the dielectric material over the first capacitor electrode and into the first capacitor electrode material; (h) depositing a capacitor dielectric material and second conductive material in the etched second capacitor electrode region; and (i) performing chemical mechanical polishing on the deposited second conductive material to yield a second capacitor electrode.
Without being limiting, the subject invention particularly employs an additional or extra photolithography masking layer for the formation or fabrication of the capacitor. This allows for cost effective manufacturing. Additionally, with a cylindrical capacitor fabricated utilizing the principles of the subject invention, the capacitance per unit area may be designed to be much larger than that of a parallel plate capacitor. This allows for more efficient use of the silicon substrate. Further, the resultant structures of capacitors fabricated in accordance with the principles of the subject invention, are planar with the top surface of the gate electrode of the transistor. This allows for a planar process topology and greater process margins.